A novel asynchronous FPGA architecture design and its performance evaluation

ABSTRACT This paper proposes GAPLA: a Globally Asynchronous Locally Synchronous Programmable Logic Array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications between synchronous blocks are controlled by 2-phase handshaking signals under bundled-data delay assumption. The size and shape of each locally synchronous block are programmable so that different modules in a design can be effectively implemented. By dividing the FPGA area into smaller blocks, the delays of long interconnect wires, which could easily dominate other delays in conventional FPGAs, only come into picture when there are communications between blocks. Therefore, each block could run at higher speed. The area overhead of adopting the GALS style in GAPLA architecture is estimated to be very small (about 7%). Experimental results show an up to 55% performance improvement compared to the conventional FPGAs

Locally compact abelian groups with symplectic self-duality

Is every locally compact abelian group which admits a symplectic self-duality isomorphic to the product of a locally compact abelian group and its Pontryagin dual? Several sufficient conditions, covering all the typical applications are found. Counterexamples are produced by studying a seemingly unrelated question about the structure of maximal isotropic subgroups of finite abelian groups with symplectic self-duality (where the original question always has an affirmative answer).Comment: 23 page

Hardware implementation of intelligent systems

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